1. Field of the Invention
The present invention relates generally to a semiconductor integrated circuit device including synchronously operating logic circuits.
2. Description of the Prior Art
In recent years, with the large scale integration of logic circuits, the difference between propagation delay times of clock signals in a clock tree for driving a synchronous circuit, i.e., the bad influence of clock skew on the high speed operation of the logic circuits, has caused serious problems.
If the large scale integration and scale down of a logic circuit proceeds, the wiring resistance of the logic circuit increases as the decrease of the wiring width thereof, so that the RC delay thereof becomes conspicuous. In such a situation, many techniques for reducing clock skew have been devised. Referring to FIGS. 11 and 12, the characteristics of the delay caused by the parasitic RC of wiring will be described below.
FIG. 11 is a circuit diagram of a semiconductor integrated circuit device comprising a clock driver 2 and an RC-distributed network 4 which is driven by the clock driver 2 to serve as a clock wiring and which comprises resistors and capacitors. FIG. 12 shows the observed waveforms D1 and D3 of voltages at nodes 5 and 7 on the RC-distributed network 4. The wiring lengths from the output S of the clock driver 2 to the nodes 5 and 7 are different. Since the wiring length from the clock driver 2 to the node 7 is longer than that to the node 5, the voltage waveform D3 at the node 7 is delayed from the voltage waveform D1 at the node 5 (see FIG. 12). As the transition in voltage proceeds, the delay amount increases regardless of the direction of the transition in voltage. Therefore, assuming that a power supply voltage is Vdd, the delay amount of the waveform D3 from the waveform D1 at an intermediate voltage (=(VH+VL)/2) when the voltage changes from VL to VH(=VL+Vdd) is Trm, the delay amount of the waveform D3 from the waveform D1 at a voltage between the voltage VL and the intermediate voltage is Trl the delay amount of the waveform D3 from the waveform D1 at a voltage between the intermediate voltage and the voltage VH is Tru, the delay amount of the waveform D3 from the waveform D1 at the intermediate voltage when the voltage changes from VH to VL is Tfm, the delay amount of the waveform D3 from the waveform D1 at a voltage between the voltage VH and the intermediate voltage is Tfu, and the delay amount of the waveform D3 from the waveform D1 at a voltage between the intermediate voltage and the voltage VL is Tf1, then the following inequalities are established.
Trl less than Trm less than Tru
Tfu less than Tfm less than Tf1
That is, as the transition in voltage proceeds, the delay amount increases regardless of the direction of the transition in voltage.
FIG. 13 is a circuit diagram of a conventional semiconductor integrated circuit device wherein clock loadings 151, 152 and 153 serving as logic circuits are connected to the nodes 5, 6 and 7 of the RC-distributed network 4 shown in FIG. 11. FIG. 14 shows voltage waveforms Di at the inputs of the clock loadings 15i (i=1, 2, 3).
Since the wiring lengths from the output S of the clock driver 2 to the nodes 5, 6 and 7, to which the clock loadings 151, 152 and 153 are connected, are different, the propagation of a clock signal is delayed as the clock signal travels from the node 5 to the node 7 as described above, so that the propagation is shown in FIG. 14. At that time, the propagation time differences Tr12 and Tf12 of the waveform D2 with respect to the waveform D1, and the propagation time differences Tr13 and Tf13 of the waveform D3 with respect to the waveform D1 are clock skews.
FIG. 15 shows another conventional semiconductor integrated circuit device. This semiconductor integrated circuit device has the same construction as that of the semiconductor integrated circuit device shown in FIG. 11, except that clock receiver circuits 401, and 402 are connected to the nodes 5 and 7, respectively. Furthermore, synchronously operating logic circuits (not shown) are connected to the respective outputs of the clock receiver circuits 401 and 402.
Inverter circuits 41 and 42 constituting the clock receiver circuit 40i (i=1, 2) are set to have an inversion threshold voltages which is the half of the power supply voltage Vdd, and 5 have input/output voltage characteristics shown in FIG. 16A. That is, as shown in FIG. 16B, assuming that the gate widths of the p-channel MOS transistor p1 and n-channel MOS transistor n1 constituting each of the inverter circuits 41 and 42 are Wp and wn, respectively, a ratio wp/wn, of the size of the transistor p1 to the size of the transistor n1 is determined so that the inversion threshold voltage is Vdd/2. In this case, assuming that the ratio wp/wn is R, i.e., wp/wn=R, then R generally approximates 2.
Assuming that the voltages at the respective inputs of the first stage of inverter circuits 411 and 412 constituting the clock receivers 401 and 402 are D1 and D3, respectively, and assuming that the voltages at the respective outputs of the inverter circuits 411, and 412 are D1B and D3B, respectively, then the input voltages D1 and D3 change as shown in FIG. 17(a), and the output voltages D1B and D3B change as shown in FIG. 17(b). That is, since the wiring length from the output of the clock driver 2 to the node 7 is longer than that to the node 5, the input voltage D3 has a waveform having obtuse leading and trailing edges in comparison with the waveform of the input voltage D1 (see FIG. 17(a)). Therefore, a time lag trm at the trailing edge and time lag tfm at the leading edge of the output voltage D3B with respect to the output voltage D1B are substantially the same as the time lags Tfm and Tfm of the input voltage, respectively (see FIG. 17(a) and 17(b)). This causes clock skew.
In a typical semiconductor integrated circuit device, the wiring lengths from the clock driver 2 to the nodes, to which the synchronously operating logic circuits or the clock receivers are connected, are fixed, and it is not often possible to reduce the capacities of the clock receiver circuits and so. In order to reduce the above described clock skew in such a case, it is required to increase the wiring width of the clock wiring or to detour to extend the clock wiring of the node near the output of the clock driver so that the delay amount at the node matches with that at the farthest node. In either case, there is a problem in that the layout area increases.
In general, the clock wiring is designed to have a large wiring width to reduce skew, and is laid out around various places on a chip, so that the increase of the wiring width or the introduction of the excessive detour wiring has a great influence on the layout area.
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a semiconductor integrated circuit device capable of reducing clock skew and preventing an increase in layout area.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor integrated circuit device comprises: a clock driver for outputting a clock signal; a clock wiring which is driven by the clock driver for transmitting the clock signal; a plurality of logic circuits which are connected to the clock wiring to be synchronously operated in response to the clock signal; and a plurality of delay circuits, each of which is provided between a corresponding one of the logic circuits and the clock wiring for delaying the clock signal, wherein a delay amount of each of the delay circuits is designed so that the delay amounts of the clock signal from the output of the clock driver to the inputs of the logic circuits are equal to each other.
Each of the delay circuits may have a resistive element. Alternatively, each of the delay circuits may have a buffer element.
According to another aspect of the present invention, a semiconductor integrated circuit device comprises: a clock driver for outputting a clock signal; a clock wiring which is driven by the clock driver for transmitting the clock signal; and a plurality of clock receiver circuits, each of which has an inverter connected to the clock wiring for receiving the clock signal, wherein the inverter is designed so that an inversion threshold voltage is different from (VH +VL)/2 when the clock signal changes from a high potential VH to a low potential VL and/or from the low potential VL to the high potential VH.
Preferably, the inverter has a p-channel MOS transistor and an n-channel MOS transistor, and a ratio of an effective size of the p-channel MOS transistor to that of the n-channel MOS transistor is different from that when the inversion threshold voltage is (VH+VL)/2.
The inverter may be designed so that the inversion threshold voltage is higher than (VH+VL)/2 when the clock signal changes from the high potential VH to the low potential VL, and lower than (VH+VL)/2 when the clock signal changes from the low potential VL to the high potential VH.
The inverter may comprise: a first p-channel MOS transistor and a first n-channel MOS transistor, the drains of the first p-channel MOS transistor and the first n-channel MOS transistor being commonly connected; second and third p-channel MOS transistors, the drains of which are connected to the source of the first p-channel and the sources of which are connected to a first power supply; second and third n-channel MOS transistors, the drains of which are connected to the source of the first n-channel MOS transistor and the sources of which are connected to a second power supply; and a delay circuit, the input of which is connected to the drains of the first p-channel MOS transistor and the first n-channel MOS transistor and the output of which is connected to the gates of the third p-channel MOS transistor and the third n-channel MOS transistor, wherein the gates of the first and second p-channel MOS transistors and the gates of the first and second n-channel MOS transistors are commonly connected to receive the clock signal to output an output signal from the drains of the first p-channel MOS transistor and the first n-channel MOS transistor.
In the semiconductor integrated circuit device, a ratio of the size of the first p-channel MOS transistor to the size of the first n-channel MOS transistor, a ratio of the size of the second p-channel MOS transistor to the size of the second n-channel MOS transistor, and a ratio of the size of the third p-channel MOS transistor to the size of the third n-channel MOS transistor may be equal to each other, the size of the second p-channel MOS transistor being smaller than the size of the third p-channel MOS transistor, and the size of the second n-channel MOS transistor being smaller than the size of the third n-channel MOS transistor.